High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure to meet the demands of the emerging compute landscape. Applications such as artificial intelligence, machine learning, data analytics, 5G, automotive, and high-performance computing are driving these demands to meet the needs of cloud computing, intelligent edge, enterprise, and client computing infrastructure. On-package interconnects are a critical component to deliver the power-efficient performance with the right feature set in this evolving landscape. Universal Chiplet Interconnect Express (UCIe), is an open industry standard with a fully specified stack that comprehends plug-and-play interoperability of chiplets on a package; similar to the seamless interoperability on board with well-established and successful off-package interconnect standards such PCI Express®, Universal Serial Bus (USB)®, and Compute Express Link (CXL)®. UCIe enables co-packaged optics that can be used to connect across servers in a Rack and Pod to realize resource sharing and dis-aggregation using CXL protocol. In this talk, we will discuss the usages and key metrics associated with different technology choices in UCIe. We will also delve into the different layers as well as the software model associated with UCIe along with the compliance and interoperability mechanisms. We will also discuss how this open standard could potentially evolve to incorporate additional usage models in the future.