The introduction of CXL has significantly advanced the enablement of memory disaggregation. Along with disaggregation has risen the need for reliable and effective ways to transparently tier data in real time between local direct attached CPU memory and CXL pooled memory. While the CXL hardware level elements have advanced in definition, the OS level support, drivers and application APIs that facilitate mass adoption are still very much under development and still in discovery phase. Even though memory tiering presents new challenges, we can learn a great deal from the evolution of storage from direct attached to storage area networks, software defined storage and early disaggregated/composable storage solutions such as NVMe over fabrics. Presented from the viewpoint of a real time block storage tiering architect with products deployed in more than 1 million PCs and servers.
CXL Memory Disaggregation and Tiering: Lessons Learned from Storage
- The basic elements of tiering software
- Primary differences between storage tiering and memory tiering
- The CXL latency problem and why tiering is needed
- The complexities of building tiering for multiple operating systems
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Modern memory, storage and content delivery systems are built out of myriad components that provide a dizzying set of parameters used to optimize their cost or performance.
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